Abstract:
During the last decades, the increase of power density in digital systems placed energy dissipation among the most critical design metrics, calling for a higher focus on ...Show MoreMetadata
Abstract:
During the last decades, the increase of power density in digital systems placed energy dissipation among the most critical design metrics, calling for a higher focus on the development of low-power optimization techniques and architectures. This paper presents some power-driven architectures for arithmetic and logic circuits, which exploit precomputation, clock gating, and pipelining to address the problem mentioned above for a 32-bit ALU. Post synthesis results show that using these techniques can lead to power savings of 36% for an integer comparator and 44% for an integer square root unit.
Date of Conference: 14-16 June 2022
Date Added to IEEE Xplore: 03 August 2022
ISBN Information: