A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters

In this work, a 12-bit, 150-MS/s, 13-steps redundant asynchronous SAR ADC achieving better than 63-dB SNDR and 72-dB SFDR with a 100-MHz Equivalent Resolution Bandwidth (ERBW) is presented. To achieve a high conversion rate without impairing accuracy, the implemented ADC features a custom sub-fF unit capacitance with mismatch calibration in the digital domain, a sub-radix-2 CDAC which introduces redundancy in the conversion, and a new version of the monotonic switching algorithm. The proposed switching procedure halves the common-mode voltage variation at the input of the comparator without requiring any additional voltage reference and without increasing the SAR logic complexity. The presented SAR ADC is fabricated in a 28-nm bulk CMOS process as part of a 6x time-interleaved converter.