A Novel Approach to Mitigate Power Side-Channel Attacks for Emerging Negative Capacitance Transistor Technology

Power side-channel (PSC) attacks have recently gained popularity in breaking into cyber-physical systems due to their non-invasiveness and proven effectiveness. In the CMOS circuit, the power dissipation when output transitions from ‘0' to ‘1' is different compared to the transition from ‘1' to ‘0'. The difference in power consumption results in input-dependent correlation, used for PSC to infer secret keys. This is the first work to investigate the impact of PSC on NCFET at the device level. We demonstrate using Gate Work Function engineering to mitigate PSC attacks effectively for the first time.