High Performance Field Configurable Data Re-alignment Engine

High performance designs involving wide data bus to achieve high throughput is a common sight in Modern SOCs. In such applications, we often encounter a requirement to perform data transfer that involves a data segment, which is smaller than the data path width. Additionally, we also need to take care of scenarios, where data segment starts at an arbitrary non-zero offset within the bus, referred to as unaligned transfers and has to be transferred to a destination that requires a different arbitrary alignment or to pack multiple segments into a single unit. Such applications, also involve a reverse requirement of extracting a segment out of the data bus and to send it separately with arbitrary alignment to the destination. These requirements are handled either in Firmware Code using basic Shift/rotate in ALU or using a dedicated Data Re-alignment Hardware in High performance applications, which takes care of incorporating all combinations of data shift / rotate / extract / concatenate operations on the fly. The resulting logic, when realized in Hardware, is usually complex in terms of routing congestion involving many levels of combinational logic, limiting their performance. Being a fixed logic, it becomes difficult to accommodate newer re-alignment requirement that was not envisioned during design phase. In this paper, we propose a novel Data Re-alignment engine that is area efficient, involves fewer levels of logic between flops and allows seamless field configurability. The proposed design is also extremely layout friendly compared to conventional designs.