Effect of Deep Level Traps on the Performance of E-Mode Recessed Gate GaN Double-Channel MOS-HEMT

Multiple channel Metal Oxide Semiconductor High Electron Mobility Transistors (MOS-HEMTs) devices are extensively studied due to their improved power density and performances along with the CMOS compatibility. Recessed gate structure enables E-mode operation with some performance drawbacks. Combining both technologies provides an opportunity to utilize the advantages of both with optimized performance. For better understanding of the Double Channel (DC) Recessed Gate MOS HEMT’s characteristics and economic fabrication, it is important to understand the heterojunction channel interfaces and their effect on device performance with respect to different operating conditions. In this study, a DC-MOS-HEMTs with gate recess is simulated and its 2DEG Density, electrostatic, transfer and transport properties are characterized. Deep Level Acceptor type channel interface traps are introduced at both channels and their effects on the HEMT device performance are studied and explained in detailed manner. From the analysis, it has been found that trap density at one channel does not have impact on the 2DEG carrier density of the other channel. However, trap density at any channel affects the on-voltage of both channels.