RTL & Physical Design Flow of Power Efficient Components of All Digital Phase Locked Loop (ADPLL)

In this paper, the physical design (PD) of components of an all-digital based low power phase-locked loop is proposed. Open-source EDA tools are used to convert a RTL design into Graphic Design System (GDSII). Tools includes like Yosys, Graywolf, OpenTimer, Qrouter, and Magic are used for the PD flow for 180nm based and 45nm based technology files in this design. An analysis of the area, power, and delay is done for the 180nm and 45nm technology files based design using EDA tools. The observed area, power, delay, and maximum operating frequency for 180nm and 45nm are 4898.80we,142.65 µW, 1180 ps, 1028.93 MHz and 160.60 µm
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,7.66 µW, 2118 ps, 1031.54 MHz, respectively. Also, 96.72% area improvement is observed for 45nm technology compared to 180nm technology.