Modeling Nanoscale Depletion Mode MESFET and Comparative Study for Different Semiconductor Materials

This paper presents a study on the modeling of nanoscale MESFET. The proposed structure uses a Schottky barrier or rectifying contact to reduce fabrication inconvenience by removing the necessity of an oxide layer in a FET. So, it can be an attractive alternative to a typical MOSFET. Modeling the structure in nanoscale ensures minimum transistor size and maximum transistor density in a chip. Ensuring the small dimension of the device, the proposed design has been simulated with COMSOL Multiphysics simulator. The paper also focuses on studying the structure with a variation of materials used as substrate. I-V characteristics like drain current vs. drain to source voltage and drain current vs. gate to source voltage of various materials are investigated. Device performance based on switching ratio is also compared in this study. By using high mobility material, a better switching ratio can be achieved. Due to fast switching, the device can find its usage in high frequency and low power applications.