Design and Development of Reliable Low Power High Speed 4-Bit Array Multiplier using High Performance 1-Bit Full Adders

Arithmetic operations of binary numbers are the key requirements for all the latest data driven technological advancements including artificial intelligence and machine learning. The present work focuses on the design and development of reliable, low-power and high speed 4-bit array multiplier using high performance mirror and transmission gate based 1-bit full adders. The performance of the proposed 4-bit array multiplier is extensively analyzed for power and delay characteristics at various operational voltages (0.7V to 1.2V) for different technological nodes ranging from 16nm to 130nm.The proposed 16nm technological node 4-bit array multiplier using transmission gate based full-adder circuit dissipates a nominal power of 5.05 µW at an operational voltage of 0.7V, while it dissipates 18.17 µW for mirror full-adder circuit. The power dissipation increases with increasing operational voltage for the proposed 4-bit array multiplier using the two high-performance full adder circuits. The proposed 16nm technological node 4-bit array multiplier yields a delay of 6.37 ps at 1.2V for mirror full adder and the delay increases to nanoseconds regime for the transmission gate based full-adder. The increased delay is might be due to presence of pass-transistors in the transmission gate based full-adder design which require precise transistor scaling at sub-nanometer technological nodes. The simulation analysis suggests the use of mirror full-adder circuit in the development of high speed 4-bit array multipliers; and transmission gate based full-adder circuits for the design of low-power 4-bit array multiplier.