Weighted Error Correcting Code (WECC) for Asymmetric Errors in STT-MRAM

As a promising non-volatile memory, Spin-Transfer Torque Magnetic RAM (STT-MRAM) has attracted the attention from both academics and industries due to its high-density, non-volatile, CMOS process compatibility and low leakage current, etc.. However, non-negligible error rate that exists in STT-MRAM should be paid attention since the MTJ device is two-terminal-ones with the same current path shared by write & read operations. And the error occurrence rate of STT-MRAM shows an obvious asymmetric, where the memory cell storing data 1 is more fragile than the cell storing data 0. This asymmetry arouses the requirement on the new strategy of error correction code (ECC). The traditional ECC approach applied on FLASH can't be used on STT-MRAM anymore. In the paper, a weighted error correction approach (WECC) is proposed, which includes the influence of the asymmetric error rate on STT-MRAM and achieves more efficient error correction. Simulation results show that WECC strategy can reduce the error rate by 3.5 times compared to the traditional BCH ECC approach. Also, the energy consumption of WECC is reduced by 3%. The proposed WECC can be used for the error correction of the novel non-volatile memories with asymmetric storing property.