Bit Error Mitigation Using Unequal Resistivity Levels in Memristors

This paper proposes a memory design to mitigate memristor bit errors. In this regard, a multi-resistance same data design has been introduced. It uses diverse resistivity levels to save the same data in various memristors, placed in a physical word block based on their location. The threshold line is also relocated and is considered as the maximum memristance instead of the middle resistivity of the memristor. Using this method, the bit errors during read/write operations occurring after read/write disturbance are significantly reduced, and overall refresh is not needed. Moreover, simulation results show read energy and performance are improved around 67% and 58%, respectively, in return for a negligible deficiency in energy and write performance. In addition, the lifetime of memory is also increased due to the reduction in refresh cycles.