Performance Analysis of 1-Bit Full Adder CMOS Using Bridge Style Logic

This paper presents the new design of CD logic based style named as Bride Logic style. Low power consumption with high performance of the circuit is one of the important factors for VLSI circuit design. The bridge logic style makes it reliable and accurate for performing complicated logic expressions. Bridge logic style uses the less number of transistors count as compared to others logic style. In this logic style, the output is pre evaluated before the input is given to pull down network. The timing window technique is analyzed which is mainly for the reduction of power dissipation i.e., reduction of the evaluation time Simulation results of Bridge logic illustrate the superiority against the conventional logic design in terms of power consumption. Area, Number of transistors count, Delay, PDP. We have performed simulation using 90nm gpdk CMOS Technology in Cadence Virtuoso.