CMOS Negative Impedance Converter Circuit with the Elimination of Parasitic Gate-Source Capacitance

A CMOS negative impedance converter (NIC) circuit with the cross-coupled topology is designed to generate negative resistance/capacitance/inductance in the frequency range between 100 MHz and 3 GHz. The proposed NIC circuit can cancel the parasitic gate-source capacitances of NMOS transistors which are the core elements of this type of topology. The negative impedance conversion capability of the circuit is shown analytically. It is also verified in AWR Design Environment using BSIM3 and BiCMOS transistor models comparatively. The circuit is tested with the loads 50Ω resistance, 5 pF capacitance and 10 nH inductance. The results show that the performance of the proposed NIC circuit is satisfactory and close to its theoretical values.