A Scalable Coarse-Grained Reconfigurable Array Based FFT Hardware Accelerator

This algorithm is computation intensive and time-consuming. To eliminate these restrictions, a FFT hardware accelerator based on the Coarse-Grained Reconfigurable Array (CGRA) is proposed in this paper. Take advantage of the dynamic reconfigurable computing architecture and the elaborate storage structure, the accelerator possesses high speed, high energy efficiency, and high scalability in supporting a wide range of FFT size. Experimental results demonstrate that the proposed accelerator achieves $4. 85.61 \times $ speed up in comparison with the state-of-the-art FPGA-based realizations.