Scheduling and Routing Synthesis for Off-Chip Time-Triggered Communication

With the increasing data processing ability of System-on-Chip (SoC), real-time systems are more and more implemented by off-chip interconnection architecture, which is small in size. Meanwhile, real-time applications demand time-triggered communication. Therefore, it is important to find a routing and scheduling approach for time-triggered messages in off-chip interconnection architecture. To achieve trade-offs between the cost of routing and scheduling while meeting the requirements of Time-Triggered Ethernet (TTE) is the main challenge for real-time communication. In this paper, we propose a scheduling and routing synthesis using an immune algorithm that is suitable for off-chip interconnection architecture. Given a set of time-triggered messages and the topology of the off-chip network, this approach is able to provide feasible routing and scheduling solutions which guarantee the schedulability of messages in off-chip time-triggered communication. Evaluation results show that the proposed approach can ensure the schedulability of all messages when the load of the network reaches 0.9, and achieves a significant improvement in runtime compared with approaches that do not consider synthesized optimization.