PSI Design Solutions for High Speed Die-to-Die Interface in Chiplet Applications

The novel design methodology is proposed to find optimal design scheme (routing structure) of die to die interface which ensures the signal quality up to 32Gbps. It explores the design solution space quickly and accurately to find optimal design parameters under PSI constraints such as channel loss and crosstalk limit. Using this design methodology, the optimized die-to-die interconnect design structure is found and implemented on silicon interposer using the obtained parameter values. The proposed approach method is proven to be effective and useful to mitigate the severe channel loss and crosstalk risk in the silicon interposer while meeting the required bandwidth of die-to-die IP implemented in chiplet application.