Chip Last Fanout Chip on Substrate (FOCoS) Solution for Chiplets Integration

In recent electronic product market, high density chiplet package integration is taking leads to the world of "more than Moore". Since breaking down from a large chip, multi-chip architectures provide high performance and low cost of electronic production. These packages are developed for the server, high performance computing, router, and switcher markets. Therefore, the integration of high bandwidth memory (HBM) devices or multiple ASIC dies requires high I/O counts and signal transmitting. For this package requirement, chip last fanout chip on substrate (CL-FOCoS) technology is adopted to integrate multiple chiplets into a single package. The high I/O density capability provides the flexibility of high performance requirement. Moreover, the chip last process induces lower non-good die loss and lower total cost of electronic production. Advanced fanout solution for chiplets integration is presented in this paper. Multiple ASICs, which includes one large ASIC with 8 small chiplets, are flip chip attached on a fanout wafer to form a fanout Chip (FOC). The FOC is a much larger size module (vs. original ASIC size), which contains 9 ASICs in total, then carry on the flip chip process to attach on an organic substrate (on substrate process), to complete the final package.Chip last approach is adopted, meaning multi layers RDL is fabricated and ensure good quality, prior to ASIC attach. The fanout process contains 3 layers of RDL with min. L/S of 2/2um, with stacking or stagger via process. Regarding fanout RDL process, the passivation via and fine line RDL would be better control on CD variation and quality judge by AOI and electric measurement, such as RDL leakage, sheet resistance and via chain resistance. For high performance requirement, hybrid bump (large and small bump pitch) is designed in ASICs. Small bump pitch is applied in the die-to-die interface for high density interconnect requirements. Large bump pitch is designed for outside communication from FOC.Regarding chip on wafer (CoW) and chip on substrate (CoS) assembly process, the fanout wafer would be better control on wafer level warpage and flatness wafer will helpful for hybrid ubump joint. On the other hand, fanout chip on substrate would be better on joint quality and CoS package warpage control by stiffener ring. After temperature cycling test, a good reliability performance of full package is demonstrated.