Study of Large Exposure Field Lithography for Advanced Chiplet Packaging

Demand for computers, GPUs and FPGAs and AI chips continues to grow as more systems demand higher computing power including AI processing and deep learning. To meet the performance and bandwidth requirements of the AI chips it is necessary to increase the chip area and/or the number of cores.However, chip area increases lower manufacturing yield and cause an increase in cost. To overcome this loss, the use of large “chiplet packages” that integrate multiple cores of a size that does not lower yield has become a major trend. Chiplet package requirements include accurate alignment of high-resolution patterns over large device areas.In this paper, we will report on our study of resolution and overlay performance across a large exposure field using the new stepper including an introduction of technology innovations supporting advanced packaging development.