Substrate Silicon Wafer Integrated Fan-out Technology (S-SWIFT®) Packaging with Fine Pitch Embedded Trace RDL

This paper presents an advanced redistribution layer (RDL) technology called embedded trace RDL (ETR) for use in the substrate Silicon Wafer Integrated Fan-out Technology (S-SWIFT
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) package. S-SWIFT packaging is designed to provide increased input/output (I/O) and circuit density within a reduced footprint and enable high reliability and excellent electrical performance. ETR is created by a novel photolithography technique and a photo-sensitive passivation material with high resolution.Since the process steps of the new ETR are reduced compared to the current process, it can provide a cost effective, multi-layer RDL in a short cycle time using existing infrastructure. ETR possess capabilities of less than 2-μm resolution and multi-layer stacking up to 6 layers. To secure stable processability with high yield, a highly uniform dielectric coating, optimum plating and planarization process were developed. To validate its integrity and reliability, an S-SWIFT package with 4-layers of embedded RDLs with stacked vias was fabricated and JEDEC standard reliability tests were performed. The S-SWIFT package passed the temperature cycling (TC), highly accelerated temperature and humidity stress test (HAST) and the high temperature storage (HTS) testing.