Heterogeneous Integration for Chiplets on FOWLP Development Line

This paper provides developments updates in the FOWLP development line for high-density heterogeneous integration chiplets applications. Up to eight chiplets designed with chip-to-chip interconnection in an extremely large FOWLP has been demonstrated. In addition, other chiplets integration arranged in side-by-side, as well as vertically integrated with face-to-face embedded EFI configurations will also be updated and discussed.