Die Bonding Solution for Flip Chip-Chip Scale Package-DIC (Digital Image Correlation) and Shadow Moiré Application

The 5th Generation wireless systems popularity will push the package development into a high performance and heterogeneous integration form. Electronic products will be thinner and smaller, high-speed, high I/O density and other characteristics. So Bump diameter and Bump pitch design will gradually become smaller or narrower to meet the bump density. Packaging will cause more semiconductor assembly process challenges, such as non-wetting & bridge issue for Die Bond process.Bump shift and warpage mismatch from X/Y/Z axis will affect FCCSP package on assembly process. It is caused by die and substrate Coefficient of Thermal Expansion (CTE) mismatch. To reduce the effect, we will combine 3D digital image correlation (DIC) technology and Shadow moiré(SM) technology to analyze three dimensional displacement, using DIC to check X/Y axis displacement and using Shadow moiré to check Z axis displacement. With that, we can find the optimum bump layout design and depend on shadow moiré result to define the high risk area of die bond with IA system (Interface analysis-analyze the gap and define the risk area between die and substrate).Combine these method, we can prevent the bump shift/warpage mismatch from X/Y/Z axis and provide an optimum solution in advance to effectively reduce the Die Bond process yield loss. Shorten NPI (New Product Introduction) development timeline to meet the growing needs of the 5th Generation wireless systems.