Design of Reliability Test Assemblies for WLCSP Solder Interconnects using Finite Element Modeling

In this study, a finite element model was designed to access inelastic strains accumulating in solder joints of a wafer level chip scale package (WLCSP) during the reflow process. The finite element model was evaluated to analyze different bump array layouts and board pad configurations such as solder mask defined (SMD) and non-solder mask defined (NSMD) to determine the most suitable configuration for thermal cycling reliability test. Maximum equivalent plastic strain and maximum principal stress were used to identify the critical bump location in the model and critical region within the bump. A package consisting of a 7x7 mm
²
die with a thickness of 300 μm directly attached to a 10x10 mm
²
printed circuit board (PCB) has been used for simulation. Size of a fully populated bump array was 18x18 bumps with 350 μm pitch. Solder joint diameter was varied from 240 μm to 270 μm depending on board pad configuration. As a result, two bump layouts i.e. 3x3 and 5x5 corner bump populations were found to cause reasonable load levels. Hence, these two bump layouts are planned for setting up the reliability test in order to obtain the solder lifetime coefficients.