Analysis and Suppression of Zero-Sequence Circulating Current in Parallel Three-Level Inverters using Improved Interleaved DPWM

This paper analyzes the switching sequence of an improved interleaved discontinuous pulse width modulation (IIDPWM). An interleaved PWM is used to improve the output current quality of parallel inverters. However, the carrier phase difference caused by the interleaved PWM inevitably generates zero-sequence circulating current (ZSCC). The IIDPWM is the interleaved DPWM applied the carrier phase shift algorithm to suppress ZSCC and has been proposed only in parallel two-level inverters. This paper proposes the IIDPWM applied to parallel three-level inverters for higher power capacity and better output current quality. The switching sequence analysis of the proposed method proves that it has significant ZSCC suppression performance even at high modulation index (MI). The effectiveness of the proposed modulation method is verified by the simulation results.