Verification of 1MHz Multisampling Disturbance Compensation Deadbeat Control for Megawatt-Level Grid-Tied Multi-level Inverter using Controller Hardware-in-the-Loop

With the rapid spread of distributed power supply systems, the impact on the stability of power systems is also increasing. As a result, the performance requirements for grid-tied inverters are becoming higher, but in MW-level grid-connected inverters, the carrier frequency is limited. In this paper, a disturbance compensation deadbeat control with 1 MHz multi-sampling method that can respond to changes in state variables between carrier interval is proposed by increasing the sampling frequency even at low carrier frequencies. FGPA based hardware controller is used to implement all the control calculation into the FPGA circuit. In addition, as a solution to the difficulty of experimental verification in mega-watt class gird-tied inverter, controller hardware-in-the-loop (C-HIL) is used to verify the control performance. Verification of the control system using the controller which is used in the actual system can be realized. The effectiveness of the proposed method is demonstrated by verifying the control system with C-HIL platform, superior characteristics was confirmed.