Examining Vulnerability of HLS-designed Chaskey-12 Circuits to Power Side-Channel Attacks

In this paper, four different versions of FPGA-based hardware implementation for Chaskey-12, a lightweight message authentication code algorithm suitable for resource-constrained devices, were generated using high-level synthesis (HLS) with different optimizations for memory and operation parallelization to examine the effects not only on the circuit area and execution time but also on vulnerability to power side-channel attacks. Through evaluation with Welch’s t-test, we disclosed how each optimization would contribute to information leakage through power consumption when no countermeasure is employed.