Digital Implementation of Level-Shifted Pulse Width Modulation for Multilevel Converters

Using digital methods for the implementation of different pulse-with modulation (PWM) strategies on multilevel converters (MLCs) has become popular among researchers during the past decade due to ease of controllability and realization. Among digital platforms, field programmable gate arrays (FPGAs) stand out to achieve this purpose due to its advantages like high clock frequency and parallel processing capability. Extensive research reveals that there is a gap in the literature in terms of detailed implementation of level-shifted PWM (LS-PWM) schemes on FPGAs. Hence, the main purpose of this paper is to fill this gap in the literature by suggesting a FPGA based digital implementation of LS-PWM schemes for MLCs. VHDL is employed to realize the architectural details of LS- PWM in this study. A comparison is held in terms of resource utilization of different LS-PWM methods within FPGA and it is revealed by simulation that three main types of LS-PWM schemes are realized successfully on FPGA.