Comparative Analysis of Charge Pumps for PLL Applications

Charge-Pump Phase-Locked-Loops (CPPLLs) are commonly used in frequency synthesis, communication system, etc. as it has a features like clock synchronization, wide range of locking, high system gain, zero static phase error, consume less power and high speed operation. In this paper, multiple Charge-Pumps (CPs) of different topologies like conventional charge-pumps, differential input charge-pump, cascade-based charge-pump and compensation-based charge-pump have been taken into consideration for analysis. A new CP with control switches to improve leakage and performance and simple OPAMP to reduce design complexity is proposed which shows better comparative result. A Phase Frequency Detector (PFD) is designed and implemented for generating the reference inputs to the above designed CPs. The designs were all given a supply voltage of 1V and reference frequency of 100 MHz. Cadence Virtuoso tool (Version IC6.7.1 ISR3) is used to implement the designs and simulations. The comparative analysis showed that the proposed CP offered better performance than the other CPs and gave <1% current mismatch, 12.5% better output voltage swing, 7.83% better power consumption, 7.3% better output noise and 14.16% reduction in area when compared to best results of other CPs.