Analysis of Power in SRAM Cell with Various Pull up, Pull down and Pass Gate Transistors

SRAM cell plays major role in many microelectronic and nano electronic devices. Low power consumption or low leakage power, high speed operations to match the recent trends are the challenges in SRAM designs. In this work, we have designed a 6T SRAM which has 6 transistors with 2 pull up, 2 pull down and 2 transistors acting as pass gate transistors, cross coupling between the pull up and pull down vertical connections helps in maintaining the sleep mode leakage power in SRAM cell. Threshold conditions can be introduced for high speed operations in SRAM. 6T SRAM is designed in cadence with 90nm technology, further the layout is drawn for 90nm technology and the output waveforms from SRAM cell layout are presented.