Random Pattern Generation and Redundancy Analysis in Memories

Designing a memory is a challenge by itself as the storage and fault occurrence is quite common in memories. Hence, fault occurrence and fault detection, corrections are major problems in memories. In this process, we have generated random 8-bit Fibonacci series for storing into memory. Further, introducing faults and detecting, correcting faults in memory locations can be carried out out using various algorithms. Simulations are carried out in Xilinx using VHDL. RTL schematic and LUTs design for the 8-bit generations are shown. Waveform for bit0 generation and the structural model 8-bit generation of bit0 to bit7 are simulated in Xilinx using VHDL and presented.