Design of Area Efficient Unified Binary/Decimal Adder/Subtractor Using Triple Carry Based Prefix Adder

Arithmetic operations of the binary numbers play a vital role in the design of General Purpose Processors (GPP), Arithmetic Logic Units (ALU), etc. Similarly, decimal addition and subtraction are most widely used in banking, financial computations and business applications. In this paper, an area-efficient Unified Binary/Decimal Adder/Subtractor design is proposed. Here, a Triple Carry Prefix Adder is used instead of Quaternary Parallel Prefix Carry Network (QPPN). It uses a triple carry operator, which reduces the area by combining three adjacent blocks to compute the group generate and group propagate signals, whereas QPPN combines two adjacent blocks. To combine three adjacent blocks, Triple Carry Prefix Adder uses two levels but QPPN uses three levels which reduce the speed. Therefore, the proposed Unified Binary/Decimal Adder/Subtractor reduces the area by 2.87% and delay by 13.23% when compared to the previous combined Binary/Decimal Adder/Subtractor.