I. Introduction
Mixed-signal integrated data converter circuits, such as time-interleaved digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) with ultra high conversion rates, demand challenging clock path circuits possibly determining the entire circuit performance. First, frequency dividers for different circuit parts are required. Secondly, several clock signal properties like common mode level, duty cycle and magnitude have to be optimized. Finally, for proper timing in clocked, time-interleaved front-end systems, the clock phase relations have to be precisely adjustable to omit intersymbol interference and ensure ideal sampling instants. Especially DACs that use the means of analog multiplexing at the DAC outputs [1] or a set of ADCs that use demultiplexing at their inputs [2], respectively, require precise relative clock timing (skew) of the single converters’ clocks. Additionally, jitter is a critical aspect determining effective number of bits (ENOB) with increasing signal frequency. Here, a low jitter clock path up to 57 GHz including a 5 bit programmable phase interpolator realized in a 28 nm fully-depleted silicon-on-insulator (FD-SOI) CMOS technology [3] allowing forward body-biasing is presented. It is a key element for paving the way to higher sampling rates of monolithic, time-interleaved data converters in CMOS. The input circuit parts at highest frequencies (fclk and fclk/2) are realized in (inductively peaked) current mode logic (CML). After level conversion, the design passes into common CMOS logic.