30-46 GHz 1.5dB IL Negative Gate Control SPDT with 24.5dBm IP1 in 130nm CMOS

In this paper a novel way of improving IP1 of SPDT switches is presented. IP1 of a SPDT generally degrades with power due to the leakage to the isolated port. Adding a negative control to the off state of the switch improves IP1 performance considerably while lowering the insertion loss. Compared to traditional series/shunt SPDT designs the negative gate control shunt SPDT provides wider bandwidth, lower insertion loss, higher isolation and higher IP1. The negative gate control SPDT outperforms traditional SPDTs and state of the art achieving an insertion loss of 1.5dB with wide band isolation (20–50GHz) better than 23dB and an IP1 of 24.5dBm in low-cost 130nm CMOS.