Optimized Design of Power Efficient FIR Filter Using Modified Booth Multiplier

Digital filters are vital a part of digital signal process. The Finite impulse response (FIR) in various signal processing applications has been employed. It has wide range of applications such as image processing, data transmission, biomedical, wireless communication networks etc. The digital finite impulse response consists of three main blocks. They are multiplier, adder, and delay. FIR filter design causes excessive area and power consumption because of multiplications is of large number. Multiplier factor is the main block in FIR filter. Various ways are delineate within the study to execute application specific integrated circuit (ASIC) in digital finite impulse response filter. High power consumption in partial product generation of the standard multiplier factor section. In planned work, the implementation of Radix-4 Booth multiplier factor and improved booth has been performed for 16-Tap FIR filter. The multiplier factor design helps to reduce the amount of steps in multiplication and additionally in digital circuits decrease the propagation delay and the power consumption. Compared to FIR filter with traditional multiplier factor results clearly indicate that power and capacity are condensed. The results show that the improved Booth multiplier based FIR filter ends up in smallest power and space, for communication purpose and FIR filter is additionally applicable.