Performance Evaluation of Fault-Tolerant Approximate Adder

The main emphasis of fault-tolerant adders is to minimize the performance metrics area, power and delay. Error resilient applications like Image processing, multimedia, and Internet of Things (IoT) accept degradation in the results providing a wide range of prospects for approximate adder’s optimization. Three designs of fault-tolerant adders Selector Based Fault-Tolerant Adder-I (SBFTA-I), Selector Based Fault- Tolerant Adder-II (SBFTA-II) and Optimized Fault-Tolerant Adder (OFTA) are proposed and implemented in this work with reduced switching activity and gate count. The proposed fault tolerant adders are further used in the design of 16-bit adders, where the upper 8-bits are realized using actual adders, and the lower 8 bits are implemented using the three proposed fault tolerant adder designs. The proposed fault-tolerant and existing approximate adders are synthesized in an electronic design automation (EDA) Tool using a 90 nm technology library. The proposed adder designs showed significantly improved performance metrics compared to the conventional techniques