Minimum Power Test Pattern Generator for Testing VLSI Circuits

Due to reduction in transistor size, test engineer facing an issue to minimize power during testing of VLSI circuits. Increased switching activity of the Circuit Under Test (CUT during testing become a crucial concern due to increase in power dissipation. Thus, the need for low power chip design has gained increasing significance. The proposed Test Pattern Generator is designed using combination of LFSR and modified Johnson counter to generate more number of test vectors. Test power reduction is achieved by using scan chain effectively to apply test vectors with minimum transition to Circuit Under Test. ISCAS’85 benchmark circuits are used for testing. Experimental results using Xilinx tool demonstrates the effectiveness of proposed method and shows up to 23% reduction with respect to MSIC and 33% with respect to LFSR in dynamic power with the impact on area overhead.