Design of High Speed Time – Interleaved SAR Analog to Digital Converter

The design approaches for high-speed SAR ADCs are discussed in this work. It’s an interleaving architecture with a fast coarse successive approximation register quantizer and a two-way time-interleaved (TI) fine SAR analog to digital converter for the channel. A process by which successive-approximation analog to digital converters convert continuous analog waveforms into discrete digital representations by searching through all possible quantization levels before finally choosing a single output for each conversation. A system using interleaved sequential approximation register analog to digital converters may consume less power, cost, and be smaller than a system using pipeline analog to digital converters. The design has been implemented on90nm CMOS which has proven to the efficiently working with the supply voltage of 1.8V.