SpMV Algorithm Based on MPI+HIP Hybrid Model

SpMV(Sparse matrix-vector multiplication) plays an important role in the fields of scientific research and engineering, but its non-merged memory access and load imbalance cause worse performance when dealing with very large-scale sparse matrices. In view of the above problems, this paper proposes a SpMV algorithm of MPI+HIP hybrid model based on the DCU accelerator, which uses on-chip high-speed storage space at a fine-grained level to reduce the hidden access latency to global memory. Through the warp reduction, the barriers of implicit synchronization and thread synchronization logic are reduced. The MPI is used at the coarse-grained level to partition the ultra-large-scale sparse matrix in behavioral units, and computational tasks are assigned to processes on the corresponding DCUs for accelerated processing. Experimental results show that, compared with the SpMV algorithm in the hipSPARSE library, the SpMV algorithm of the hybrid programming model achieves an increase of speedup from 4.34 to 6.44, which significantly improves the parallel efficiency.