Optimized Implementation of PRESENT 8-bit S-box structure in Secure Adiabatic Logic

Adiabatic logic is one of the prime solutions to resist the hardware device against side channel power analysis security attacks. Adiabatic circuit design technique possesses attractive energy-efficient and security characteristics which makes them suitable for lightweight devices. Design of an 8-bit S-box from the 4-bit S-box definition of the PRESENT lightweight cipher definition has been attempted with optimal number of stages. This paper also presents the circuit level implementation of the 8-bit S-box circuit with appropriate transistor sizing to achieve security characteristics using the existing secure Charge Balancing Symmetric Pre-Resolve Adiabatic Logic (CBSPAL). Secure CBSPAL provides a uniform current waveform irrespective of the input data transitions. Power analysis robustness against side channel attacks has been analyzed with one round circuit realization of PRESENT-80 algorithm in both CBSPAL and static CMOS logic. CBSPAL based S-box implementation demonstrates 83% of energy saving per cycle in comparison against the static CMOS counterpart at 12.5 MHz. Post layout simulations of the circuit have been carried out in Cadence® Virtuoso environment using UMC 90 nm technology operating at 12.5 MHz operating frequency. The CBSPAL is more effective for frequencies in the MHz band.