Geometrically Dependent Space Charge Modulation and Quasi-saturation Effect in Superjunction-LDMOS Device

Increase in the demand of smart power technologies has posed a restriction on the breakdown voltage of the laterally diffused MOS (LDMOS) transistors. Superjunction-LDMOS devices have shown to offer a low on-resistance while extending the off-state breakdown voltage by the virtue of increasing depletion area in the drift region. This makes them highly suitable in fast switching applications. While they display an outstanding OFF-state performance, these devices severely suffer from space charge modulation (SCM) leading to quasisaturation (QS) effects under high current conditions. This not only affects the operation of the device, but also degrades its safe operating area. Thus, designing such devices in order to meet the off-state requirements while mitigating SCM/QS effect is challenging. Design of a superjunction (SJ) implant in the drift region is reliant on the key process and geometrical variables such as doping, thickness, position and length of the implant, as well as, on the layout parameters like drift-doping and driftscaling. These device design parameters can be optimized individually or in combination of individual parameters in order to enhance the performance of the device. This work focuses on developing an elaborate understanding of the impact of geometrical parameters on the SCM/QS effects while proposing design guidelines aiming to mitigate these ON-state operation challenges and maximize the device performance.