PCB Layout for Chip-Scale Package GaN Fets Optimizes Both Electrical and Thermal Performance

The half-bridge comprising two switches and a high frequency bypass capacitor forms the basic building block of most power conversion applications. Prior work has shown how to design a printed circuit board layout for this building block that minimizes power loop inductance using Gallium nitride (GaN) FETs in chip-scale packages (CSP) to minimize switching losses. Under some operating conditions, this layout may create thermal bottlenecks that limit performance. Removal of some implicit assumptions allows additional design freedom which is used to derive a new layout with equal or superior electrical performance and greatly improved thermal performance without additional penalties. Initial experimental evidence shows a temperature rise reduction as high as 30%, allowing large gains in power density.