A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process

The DRAM interface development to achieve a higher bandwidth has been requested according to the advance in massive computing technologies. Multi-level signaling, PAM-4 for example, is one of the most promising ways to address the requirement to extend the per-pin data rate without increasing clock frequency [1]. This paper suggests a single-ended PAM-4 transmitter for DRAM interface which requires high-speed operation. A 4-to-1 MUX based 2-tap feedforward equalizer (FFE) for bandwidth extension is used to mitigate the channel loss and inter-symbol interference (ISI). The impedance of each PAM-4 signal level can be controlled separately by applying thermometer switching in the main driver to achieve precise matching. The output driver of PAM-4 transmitter is optimized to have high linearity for operation of both low-voltage swing terminated logic (LVSTL) and pseudo open drain (POD). Also, a new timing skew training scheme for each PAM-4 signal level is developed to adjust timing for reducing clock skew in the internal path caused by PVT variations and bit error ratio (BER) increased by the non-linear characteristics of receiver. In addition, low power maximum transition avoidance (LPMTA) encoding is applied to decrease energy consumption of output driver. The prototype chip is fabricated in a 28nm CMOS process with adjusted channel length, not applying a minimum channel length, to mimic 10nm class DRAM process conditions. It is confirmed that propagation delay time (TPD) and
$\mathrm{I}_{\text{dsat}}$
of prototype chip are well correlated with the parameters obtained by 10nm class DRAM process. Finally, 1.67-pJ/b of energy efficiency with 1.2V supply is measured at 60-Gb/s/pin with optimized single-ended PAM-4 transmitter.