Cell Stability and Write Improvement of 2T (Footprint) Stacked SRAM

Stacking 4 n-type vertical gate-all-around transistors (VFETs) on 2 pFinFETs can scale down a 6T SRAM bitcell into the footprint of only 2 transistors. The minimum operation voltage (V
min
) considering workfucntion (WF) variation can be reduced to 0.59V by tuning pFET fin height (H
fin
) to 15nm and nFET gate length (L
gn
) to 20nm without increasing bitcell area. Applying the negative bitline (NBL) level of -80mV can further increase the write speed by 10%.