Test vector generation and testing of TMS320C6745 DSP for Launch Vehicle Applications

Devices use in Launch Vehicle needs to be thoroughly tested before integrating to hardware as the cost or penalty of a failure detected later at system level checks is much more than 100 times that of earlier detection at device level. This paper deals with generation of test vectors for testing of TMS320C6745 floating point DSP, used for computing Navigation parameters of Launch Vehicle. Accurate computation of these parameters is crucial to the success of the launch vehicle. Thorough testing of the processor is to be ensured before use in launch vehicles. The device has to be tested in a standalone environment so that no other elements contribute to any deviation observed during testing. The test cases are generated to address various failure modes of the processor. The test vectors and timing files are generated satisfying the stringent timing requirements of the processor. It is also important to verify that the processor meets the data sheet specifications with respect to timing. The boot interface was configured in VHDL and a test bench was developed for passing the boot and test code into the internal RAM. All possible combinations of instructions and data paths were written in assembly language and simulated using Code Composer Studio (CCS) for the expected result. The output of CCS was converted into RAM loadable format (machine code) using AISgen tool by Texas Instruments. VLSI tester compatible test vectors were generated from the machine code using VHDL model of External Memory Interface A (EMIFA) interface. The outputs from the device were compared against the expected output generated by the CCS-Simulator. The vectors also contain the expected response from the processor as obtained by simulation.