Design and Implementation of an Efficient CMOS Operational Amplifier

Current trend in the design of many amplifier circuits, comparators, converter architectures, regulators and many more is towards low power operation and high operating speeds with optimized area. The usage of low power devices are increasing at an unprecedented rate because of the emerging applications in system on chip devices such as cellular mobile phones, microcontrollers used in internet of devices and many other biomedical applications. CMOS technology is the most predominant technology for the design of op-amp based circuits and these op-amp circuits are ubiquitous and found everywhere in the design of analog integrated circuits. In this work, a 2-stage CMOS operational amplifier is designed, simulated and analyzed for different specifications. Lower VDD values entail small input voltage ranges and hence the circuit becomes more susceptible to noise due to various design methods associated with the circuit. In this paper a CMOS two-stage operational amplifier is designed using hands approach, simulated and the important specifications are analyzed. The op-amp is designed for a given set of standard specifications and simulated using CMOS 180nm technology at VDD of 1.8V DC. After analysis of the simulated waveforms, the important parameters such as Phase margin, slew rate, gain, and CMRR are calculated.