Distributed Sorting Architecture on Multiple FPGA

FPGA has demonstrated promising performance in high throughput data sorting. Data compression techniques are adopted to exploit the redundant information between subsequent values in a sorted dataset. However, the standalone FPGA design inhibits the scalability to handle the growing dataset. Moreover, previous data compression techniques in data sorting lack versatility to support various ranges of data. This paper proposes the design of a distributed sorting accelerator on multiple FPGAs and introduce a Configurable Compressed Array to handle the various data widths. The experimental results have shown that the proposed design attains 3.69x enhancement when compared to the previous design.