On Superior Hot Carrier Robustness of Dynamically-Doped Field-Effect-Transistors

We simulate relative changes of the saturation drain current during hot-carrier degradation (HCD) in dynamically-doped (D2) and "traditional" planar complementary metal-oxide-semiconductor (CMOS) field-effect-transistors (FETs) of gate lengths and doping profiles. To achieve this goal, we use our physics-based model for HCD validated against experimental data from a broad range of transistor architectures (which include but are not limited to planar, fin, and nanowire FETs). These simulations show that at lower gate voltages of Vgs ≤ 0.9 V (i.e. covering the operating regime) D2 FETs have superior HC reliability compared to their CMOS counterparts, while at Vgs > 1.0 V the CMOS FET begins to be more reliable (at shorter stress times, however, the D2 device is still superior). Under these low stress voltages, HCD is governed by the multiple-carrier process of bond dissociation controlled by the carrier concentration (rather than energy), which has different Vgs dependences in D2 and CMOS FETs. Based on conducted calculations, we suggest that, in addition to better performance and scalability compared to the CMOS counterpart, the D2 FET has also superior hot-carrier reliability.

I. Introduction

Recently proposed dynamically-doped (D₂) field-effect-transistors (FETs) [1] have the gate contact placed at the opposite side of the FET with respect to the source/drain contacts (Fig. 1, top panel). This device topology enables faster scaling by exploiting the space used to separate source/drain and gate contacts employed in the "traditional" planar complementary metal-oxide-semiconductor (CMOS) architecture sketched in Fig. 1, bottom panel.