New Insight into the Aging Induced Retention Time Degraded of Advanced DRAM Technology

In advanced DRAM process node, buried-channel-array transistor (BCAT) in cell-array will generate additional leakage during long-term read/write operations, leading to data retention time reduction. In this work, we designed the accelerated aging test in wafer level and proposed aging leakage model. Based on Monte Carlo simulation, we predict data retention time degradation (especially tail distribution) of high-capacity DRAM under long-term operating conditions. By adding aging leakage model into conventional retention time simulation flow, the data retention time at different operation time can be predicted. It was found that the aging can degraded data retention time in tail distribution around 13% in 10 years. This work is thus helpful to the refresh scheme development considering aging effect.