Impact of TSV on TDDB Performance of Neighboring FinFET with HK/IL Gate Stacking

It is well known device parameters like mobility can be significantly affected by the stress induced by TSV in 3DIC. For the sake of long-term application, the impact of TSV stress on device reliability also requires attention. This study presents detailed characterization and analysis of TDDB performance of FinFET devices placed in the neighborhood of TSV. It is found the TDDB lifetime of the devices stressed under substrate injection mode could be seriously worsened by neighboring TSV, while that of the devices stressed under gate injection mode only shows moderate degradation. It is proposed the defect generation in high-K layer, which controls the TDDB performance under the former stress mode, may be more sensitive to mechanical stress than that nearby IL/Si interface which dominates under the latter mode. It can be ascribed to considerable charge trappings in HK during stress, which could significantly lower the stiffness of Hf-O and thus reduce the energy required for defect generation under the impact of the stress induced by TSV. It also shows the impact of TSV on TDDB has no considerable orientation dependence. The study suggests careful characterization of the reliability, other than the performance, of the devices nearby TSV with specifically designed test structure, is essential for evaluation of TSV-enabled 3DIC.