Correlated Effects of Radiation and Hot Carrier Degradation on the Performance of LDMOS Transistors

Over the past few decades, power electronics devices have found numerous applications, including high energy physics, drones, space electronics, etc. It is well-known that the devices used in these applications are often subjected to a high dose of radiation, and unlike traditional applications, it is not possible to frequently replace these power FETs (e.g., LDMOS). Therefore, it is essential to accurately predict the long-term integrated degradation of these power FETs in the presence of radiation. In this paper, we: (a) expose LDMOS transistors to various Total Ionizing Dose (TID) of gamma radiation and characterize the degradation in terms of threshold voltage shift (ΔV
TH
), subthreshold slope (ΔSS); (b) quantify the dose- dependent generation of interface traps (ΔN
IT
) and trapped charges (ΔN
OT
) using a novel charge pumping technique; (c) introduce hot carrier degradation (HCD) models to explore the physical origin of the defects and their correlation with TID; and (d) establish the universality of the degradation kinetics and illustrate that the model and inferences drawn from the findings in this paper can be applied to other LDMOS devices as well. This analysis takes us a step closer towards a generalized TID-HCD model for power FETs that incorporates all sources of variation (electrical, thermal, and radiation) during device operations.