Area Optimized Implementation of Galois Field Fourier Transform

Fourier transform is the conversion of signal from time domain to frequency domain. FFT is a modified version of DFT, where the computation is fast when compared to DFT. Performing FFT over finite field is the main task. Finite fields are fields which consists of finite elements. Performing FFT over finite field is called Galois field FFT. In this project, a method to implement the Galois field FFT without multipliers is done for three architectures namely the SIPO (Serial In Parallel Out) architecture, PISO (Parallel In Serial Out) architecture and optimized SIPO architecture. It is observed that a reduction in area of 42% in 'SIPO and PISO architectures' and 50% reduction in area in ‘optimized SIPO architecture’ is achieved on implementing multiplier less design by replacing the wrap around carry addition with XOR multiplexer full adder instead of conventional full adder.