Realization of Foreground Calibration and Correction of Pipelined ADC Based on 2.5-bit Stages

This work is devoted to foreground calibration of the pipelined ADC by the least-squares method. A 12-bit pipelined ADC based on 2.5-bit stages is chosen for research. Modeling and implementation of the calibration is performed in the MATLAB/Simulink. In the process of work the modeling of 12-bit pipelined ADC based on 2.5-bit stages, realization of the calibration scheme with the development of script in MATLAB, allowing to calculate calibrating coefficients, and also, the comparative analysis of calibration schemes with use of various final flash stages is carried out. The corresponding dependences of the static and dynamic characteristics when varying the DC gain of Op-Amp (μ
0
) for each stage with μ
0
stage scaling are plotted. This work allows estimating ranges of variation of DC gain for each stage, and also, can be a basis for the further physical realization of the given digital calibration for ADC based on 2,5-bit stages.